
REV. A
–5–
AD5533B
SERIAL INTERFACE TIMING DIAGRAMS
1
2
3
4
5
6
7
8
9
10
t
1
t
2
t
3
t
4
t
5
t
6
MSB
LSB
SCLK
SYNC
D
IN
Figure 3. 10-Bit Write (ISHA Mode and Both Readback Modes)
2
1
3
4
5
6
7
8
9
10
11
12
13
14
MSB
LSB
SCLK
SYNC
D
OUT
10
t
11
t
10
t
1
t
2
t
4
t
8
t
9
t
7
Figure 4. 14-Bit Read (Both Readback Modes)